Linear power amplifiers, such as CDMA or WLAN power amplifiers, typically require a bias reference voltage in order to set the quiescent operating current of the amplifier. Standard practice in bias circuit design is to set a current density in a small transistor and then mirror that current density to a larger RF amplifier transistor.
FIG. 1A is a circuit diagram of a conventional bias circuit 100, which is used to bias an RF amplifier transistor 110 of a linear power amplifier. Bias circuit 100 includes enhancement mode field effect transistors 101–102 and resistor 103, which are connected as illustrated. Bias circuit 100 applies a bias voltage VGSOUT to the gate of RF amplifier transistor 110, thereby causing a quiescent DC bias current IB to flow through transistor 110.
The drain of transistor 101 and a first terminal of resistor 103 are coupled to receive a regulated voltage VREG. The second terminal of resistor 103 is coupled with the gate of transistor 101 and the drain of transistor 102. The source of transistor 102 is grounded. The source of transistor 101 is coupled with the gate of transistor 102 and to the gate of RF amplifier transistor 110.
The regulated voltage VREG causes transistors 101 and 102 to turn on, such that the bias voltage VGSOUT is applied to the gate of transistor 102, and a current IA flows through transistor 102. Because the bias voltage VGSOUT is also applied to the gate of RF amplifier transistor 110, the current density of current IA is mirrored to RF amplifier transistor 110, thereby causing quiescent DC bias current IB to flow through transistor 110. It is understood that the gate of RF amplifier transistor 110 is also coupled to receive an RF input signal (not shown), and the drain of RF amplifier transistor 110 is used to provide an RF output signal (not shown).
Bias circuit 100 exhibits sensitivity to variations in the applied voltage, VREG. The regulated voltage VREG is controlled within a predetermined voltage range (e.g., 2.75 to 2.95 Volts for a 2.8 Volt system). Consequently, a precise voltage regulator circuit (not shown) is used to provide the regulated voltage VREG. Such a voltage regulator is an additional expense and undesirably adds to the circuit complexity.
Bias circuit 100 also exhibits sensitivity to variations in temperature. As the temperature increases, the bias currents IA and IB undesirably decrease, thereby undesirably changing the biasing of RF amplifier transistor 110. Bias circuit 100 also lacks a control interface for changing the quiescent DC bias current IB.
In addition, the drain of RF amplifier transistor 110 is typically coupled to receive a battery voltage VBATT, which is not as constant as the regulated voltage VREG. Variations in the battery voltage VBATT result in changes in the quiescent DC bias current IB. FIG. 1B is a graph 120 that illustrates the manner in which the quiescent DC bias current IB changes in response to changes in the battery voltage VBATT.